In many integrated semiconductor circuit arrangements, different semiconductor circuit regions are formed in the region of a semiconductor material. These different semiconductor circuit regions provide different functions during operation of the integrated semiconductor circuit arrangement. Therefore, these semiconductor circuit regions are generally also constructed and patterned differently. These different structures also have to be taken into consideration in the context of the respective fabrication process.
It is thus provided, by way of example, that the different semiconductor circuit regions of the integrated semiconductor circuit arrangement are formed with different contacts with regard to their contact-connection among one another or else externally. These contacts may differ for example with regard to the layer thickness of the materials used for the contacts, in particular of the metallizations used.
Since, by way of example, control circuit arrangements or logic circuits have a relatively low power consumption, for the formation of contacts in circuit arrangements of this type a comparatively small layer thickness suffices for the metallization layer provided and is expedient with regard to miniaturization and high packing density in this circuit region.
In addition to the contacts, the wiring interconnects represent essential elements of a logic metallization. In particular, the width and the spacing of the interconnects are among the crucial factors for the packing density that can be achieved.
On the other hand, specific other circuit regions may exhibit a comparatively quite high electrical power consumption which is correspondingly also imparted by contacts that are to be dimensioned more generously and metallization layers made correspondingly thicker. When forming the metallizations necessary for ensuring the respective layer thicknesses and functionalities, the functionality of the respectively underlying structures must remain unimpaired. However, this cannot always be ensured to a sufficient extent in the case of conventional patterning methods and in particular in the case of the respective process steps for forming different metal layer thicknesses.